Conventionally, a patent literature 1 has proposed an SiC semiconductor device that aims to restrict breakage of a gate insulation film in a MOSFET with a trench gate structure and to improve surge withstand (avalanche resistance) of the element. Specifically, a p+ type deep layer is provided to a position lower than the bottom surface of the trench, between trench gate structures, and is further deepened at a middle of a cell region. By forming the p+ type layer in this manner, concentration of an electric field at the bottom of the trench, when the MOSFET is turned off, is alleviated, and breakage of the gate insulation film is restricted. Further, since the p+ type deep layer is further deepened at the middle of the cell region, the surge withstand of the element is increased.
Also, a patent literature 2 has conventionally proposed a Si semiconductor device that enables reduction of an on-state resistance in a MOSFET with a trench gate structure. Specifically, the Si semiconductor device has a super junction (hereinafter referred to as the SJ) structure in which n type columns for forming n type drift layers and p type columns are alternately arranged, under the trench gate structure. Since the SJ structure is provided in this manner, when the MOSFET is turned off, an electric field is evenly applied in the SJ to reduce the concentration of electric field. When the MOSFET is turned on, since a current path passing through the SJ structure is formed, the on-state resistance can be reduced.